1. Field of the Invention
This invention is related to the provision of a power-on reset signal for electronic circuits.
2. Description of the Related Art
Power is often supplied to electronic systems in a gradual fashion for a number of reasons, e.g., the need to limit in-rush currents, limits on power availability, etc. During the time that power gradually "ramps up", i.e., the power supply voltage increases to its final value, circuitry may toggle somewhat randomly, leaving an entire system in an unknown state when power has been fully supplied to the system. Furthermore, the rate at which power is supplied varies from system to system, as does the final value of the power supply voltage.
Power-on reset signals are used to ensure that an electronic circuit does not begin operation until the power supply voltage reaches a level that permits proper operation. Digital circuitry, from the lowest level of integration such as the "glue" logic required to provide an interface between complex digital systems, to the highest levels of integration exemplified by the most complex microprocessors available, requires an "all clear" signal that indicates to the circuitry when operation may safely commence. Without such a signal the somewhat random toggling of digital circuitry that occurs during the time that power is gradually applied to the system could be interpreted as meaningful data or instructions, with possibly catastrophic consequences. A power-on reset signal may be employed to place registers and other circuits in a predetermined state, to provide a baseline from which to operate and, possibly, to suppress undesirable output signals.
FIG. 1 illustrates a conventional approach to creating a power-on reset signal. A delay circuit 2 includes a resistor 3 and a capacitor 6 connected in series between a positive voltage supply terminal V.sub.dd and a negative voltage supply terminal nominally designated as ground (gnd), with the resistor/capacitor (RC)'s tap connected to the input of an inverter 4. The capacitor 6 is connected between the inverter input and ground. As the power supply voltage (between Vdd and ground) increases, the tap voltage of the RC circuit follows it. Once the RC tap voltage reaches the input HI threshold voltage of the inverter, the inverter output goes LO, thus providing an active low power-on reset signal which, ostensibly, indicates that the power supply voltage has reached a level which is acceptable for normal circuit operation.
In fact, this circuit provides the power-on reset signal only indirectly. The voltage at the input of the inverter 4 does not directly track the power supply voltage. This is, the voltage at the inverter input is not a fixed ratio of the power supply voltage; rather it is a delayed version of it. The voltage at the inverter input depends upon the RC time constant, not directly upon the input voltage. Some RC time constant after Vdd passes the inverter's input threshold, the delayed version of the power supply voltage at the inverter input reaches the inverter's input HI threshold voltage. If the capacitor 6 is too small, the input voltage could reach the inverter's threshold before the power supply voltage has reached an adequate level. Because it is important to be sure that the power supply voltage has reached its minimum acceptable level before commencing operation, the capacitor 6 is often chosen to be quite large. Consequently, the resistor 3 and capacitor 6 are typically large, discrete components.
One problem with using a large capacitor is that the power-on reset circuitry must respond to disturbances to the power supply that, although brief, may be of sufficient magnitude to upset and invalidate the logic states of the circuitry. To accommodate these limited-duration power supply disturbances, often referred to as "brown outs", a diode 7 is connected across the resistor 3 so that it is reverse-biased during normal operation, but rapidly drains the capacitor 6 when the power supply voltage falls more than a diode drop below the voltage across the capacitor.
Even with the addition of the diode, however, the capacitor's selection represents a compromise between a capacitor that is large enough to assure a valid reset signal for the initial application of power, whether rapid or gradual, and one that permits a response to relatively brief power disturbances. Because it is impractical to produce large capacitors within integrated circuits (ICs) and because the rate at which power is applied to a system varies widely from application to application, this conventional circuit requires the use of external components, i.e., components not located within the IC, with all their attendant cost and reliability problems.
A complicating factor is that, in complementary metal-oxide-semiconductor (CMOS) circuits employing p-channel and n-channel field effect transistors (FETs), the threshold voltages for operation of the p-channel and n-channel devices are generally independent of each other, and can vary widely within a range of approximately 0.6-1.2 volts due to processing variations. This makes it very difficult to predict an accurate level for the termination of a power-on reset signal. If the signal is terminated at a voltage below the level at which all of the FETs are operative, the circuit may not function properly. If it is terminated significantly above the threshold levels, any circuit operation at all is sacrificed until the reset termination level is reached.
For the forgoing reasons, there is a need for a power-on reset indicator that eliminates external components, improves reliability, reduces cost and ensures, regardless of the rapidity with which power is supplied to the circuit, that the power supply voltage has reached a safe operating level before indicating to other circuitry that operation may commence.
A power-on reset circuit that satisfies these requirements is disclosed in U.S. Pat. No. 5,883,532 to Bowers and assigned to Analog Devices, Inc., the assignee of the present invention. In this patent a power-on reset circuit initiates a reset signal when the power supply voltage rises above a reset initiation level. The reset signal is terminated by a circuit that includes p-channel and n-channel FETs (PFETs and NFETS), having respective threshold voltages Vtn and Vtp, when the power supply voltage rises above the greater of Vtn and Vtp, plus an offset voltage that allows for fabrication tolerances.
While this approach is an improvement over prior power-on reset circuits, it is complicated to fabricate because it mixes CMOS reset circuitry with bipolar circuitry used to establish the voltage offset and to initiate the reset signal. This mixing of circuit technologies also adds to the fabrication cost.